System design is dependent upon three things: tools, methodology and language. VHDL is the VHSIC (Very High Speed Integrated Circuit) hardware design language used to describe the structure and behaviour of digital electronic hardware such as ASIC and FPGA designs. An international standard, it is defined by the SystemVerilog LRM (Language Reference Manual) and regulated by the IEEE (Institute of Electrical and Electronic Engineers.)
VHDL language specifically operates simulation and synthesising tools, but users are not limited to one description style, and hardware designs can be described via any method, e.g. from the top down, bottom up or both ends to the middle. Although the language itself is standardized, the hardware designer can choose the tools and methodology.
Hardware can be described by the VHDL language in a number of abstract ways. When applying VHDL to advanced ASIC and FPGA design, there are three levels of abstraction: algorithm, RTL (Register Transfer Level) and gate level. They are identified in terms of timing.
RTL represents the input, and GL the output, of synthesis. The algorithm is a set of commands carried out in sequence to perform a task, and does not have inputs, outputs, a clock or detailed delays. However, behavioural synthesis tools are available which enable VHDL input to occur. This can be constrained via an algorithmic clock.
RTL description encompasses a clock, which allows scheduled operations to occur in specific cycles, but without detailed delays. Again, tools are available to increase flexibility. Gate level description is technology orientated, describing a network of gates and registers, and contains delays.
We at Enventure Technologies offer a wide range of value engineering services, including complex FPGA programming and VHDL design.