Don’t get cold feet over FPGA design

PCB and ASIC designers constantly have to find new environmental compliance solutions for their products. Alongside RoHS, REACH and WEEE directives is the energy compliance issue, balancing minimal power consumption with maximal system output. To FPGA programming engineers, this has posed a challenge.

CFD and thermal analysis tools aid system design and reduce costs. Added to these are a number of power analysis tools, which are making a serious impact on the market. Power consumption has become an important consideration in embedded firmware, and the way in which the results are interpreted can have a significant effect on performance and efficiency. However, FPGA designers have to understand how the power consumption data patterns relate to the chips they use, for both specific clock cycles and entire computations. Many engineers base their analysis on specific power component numbers, rather than the entire power profile of the system. Not seeing the broader picture can lead to system designs which are energy inefficient – or appear to be.

This was demonstrated during development of systems implementing the Actel IGLOO low-power FPGA design. When power analysis was conducted on a single cycle basis, silicon chip consumption was seen to vary widely, with a different power number for each of the systems into which it was embedded. If only single clock cycles were considered, the FPGA often appeared to have poor energy efficiency. However, when the entire data spectrum pattern was examined, and power-down switches and alternative power modes added to the system designs, the results were good.

We at Enventure Technologies have many years’ experience in the field of DSP programming and FPGA design, offering comprehensive solutions for system analysis and PCB layout.

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